1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. More particularly, the present invention relates to a structure of the input and output circuit cell.
2. Description of the Related Art
As shown in FIG. 7, which is a view showing an outline of the arrangement of the flip chip LSI, the flip chip LSI includes: probing pads 2 arranged in the periphery of the chip; and LSI peripheral circuit elements 9 such as input and output circuit cells 3 arranged in the inner region of the chip, electric power supply cells 4 for the input and output circuit, and electric power supply cells 6 for the LSI inner logic circuit for supplying an electric power source voltage to the LSI inner logic circuit 5, wherein these LSI peripheral circuit elements 9 are arranged at a predetermined pitch, and the LSI inner logic circuit 5 is arranged in the inner region of the LSI peripheral circuit elements 9.
Further, on the surface of the chip 1, the air pads 7 connected to the electric power source wiring of the flip chip package and the rearrangement wiring 8 for connecting the area pads 7 to the LSI are arranged. The electric power source lines for supplying an electric power source voltage to drive these circuit elements are an electric power source line 10 for the LSI peripheral circuit, which is arranged in an upper portion of the LSI peripheral circuit element 9, and an electric power source line 7 for the LSI inner logic circuit arranged in the periphery of the LSI inner logic circuit 5, and these electric power source lines are arranged being electrically separate from each other. In this case, a package including a ball grid array (BGA) formed in the stiffener is used for the flip chip package.
An electric power source voltage is supplied to each circuit element in the LSI chip when the device is operated and also when the device is subjected to a product inspection. Concerning the product inspection, there are provided a probing inspection, which is conducted in the wafer stage, and a finished product inspection conducted after the completion of assembling. In the case of the finished product inspection conducted after the completion of assembling, the product is operated by electric power, the frequency of which is the same as the actually used frequency, and the input and output time of a signal is inspected. In this case, for the object of judging the result of making the LSI chip from the viewpoints of the function and performance, it is necessary to supply a sufficiently high intensity of electric power to both the LSI peripheral circuit elements 9 and the LSI inner logic circuit 5.
However, as the scale of LSI has been recently enlarged, IR drop of the electric power source causes a problem. In order to reduce IR drop, the following method is adopted. An electric power source voltage, which is supplied from the flip chip package, is supplied to the LSI peripheral circuit element 9 and the LSI inner logic circuit 5 via the area pad 7 arranged on the rearrangement wiring layer located on an upper face of the metal wiring layer of the LSI chip.
On the other hand, in order to judge the result of the manufacturing process, the probing inspection is conducted before mounting. In this probing inspection, in general, DC inspection for inspecting the result of manufacturing a transistor is conducted such as a measurement of an output current of the input and output circuit and a measurement of a leak current. These measurements of measuring electric currents are conducted when the toggle ratio of the inner logic circuit is made to come close to 100% which is called a scan test. In this case, an electric power source voltage supplied from the probing inspection device via the probing pad arranged in the periphery of the LSI is taken into the electric power supply cell and supplied to the LSI peripheral circuit element 9 and the LSI inner logic circuit 5, and the self test is made.
The structure and operation of the electric power source cell 4, which is the peripheral circuit element 9 of the LSI flip chip 1, will be explained together with the area pad 7, the probing pad 2 and the LSI peripheral circuit electric power source line 10 on the LSI peripheral circuit element 9.
FIG. 8 is a view showing an outline of the conventional input and output circuit electric power supply cell. In this case, the input and output circuit electric power supply cell 20 includes: an input and output circuit electric power source VDDQ supply cell 20a; and an input and output circuit electric power source VSSQ supply cell 20b. FIG. 9 is a view showing the input and output circuit electric power source VDDQ supply cell 20a, and FIG. 10 is a sectional view taken on line B-B′. FIG. 11 is a view showing the input and output circuit electric power source VSSQ supply cell, and FIG. 12 is a sectional view taken on line B-B′.
The input and output circuit electric power source VDDQ supply cell 20a is composed of an electric power source input port 21, an electric power source supply port 22, an electric power source wiring 23 and a surge protecting circuit 24 between the electric power sources. The electric power source input port 21 is connected to the probing pad 26 by the wiring 25. Further, the electric power source input port 21 is connected to the area pad 27 on the rearrangement wiring layer, which is located in an upper portion of the LSI chip 1, by the rearrangement wiring 28. The electric power source supply port 22 is connected to the LSI peripheral circuit electric power source line 29 by the electric power source wiring 23 in the cell. The input and output circuit electric power source, which has been inputted from the area pad 27 and the probing pad 26, is supplied from the electric power source input port 21 to the LSI peripheral circuit electric power source line 29, which is arranged on the LSI peripheral circuit element 9, via the electric power source wiring 23 in the cell and the electric power source supply port 22.
FIG. 11 is a view showing an outline of the input and output circuit VSSQ electric power supply cell 20b, and FIG. 12 is a sectional view taken on line B-B′.
In this case, one different point of the input and output circuit VSSQ electric power supply cell 20b from the input and output circuit electric power source VDDQ supply cell 20a is described as follows. In the input and output circuit electric power source VDDQ supply cell 20a, the signal wiring 23 composed of the first layer metal directly reaches the electric power source input port 21 so that it can be arranged from the electric power input port 21 to the electric power source supply port 22. On the other hand, in the input and output circuit VSSQ electric power supply cell 20b, the signal wiring 23 composed of the first layer metal reaches the electric power supply port 22 via the LSI peripheral circuit electric power source line 29 composed of the second layer metal. The other points are the same, and like reference characters are used to indicate like parts.
FIG. 13 is a view showing an outline of the LSI inner logic circuit electric power supply cell. FIG. 14 is a view showing an LSI inner logic circuit VDD or VSS electric power supply cell, and FIG. 15 is a sectional view taken on line A-A′. These views are the same as those described before. The LSI inner logic circuit electric power supply cell 30 is composed of an electric power source input port 31, an electric power source supply port 32, an electric power source wiring 23 and a surge protecting circuit 34 between the electric power sources. The electric power source input port 31 is connected to the probing pad 36 by the wiring 35. Further, the electric power source input port 31 is connected to the area pad 37 on the rearrangement wiring layer, which is located in an upper portion of the LSI chip, by the rearrangement wiring 38. The electric power source supply port 32 is connected to the LSI inner logic circuit electric power source line 39 by the wiring 43. The LSI inner logic circuit electric power source, which has been inputted from the area pad 37 and the probing pad 36, is supplied from the electric power source input port 31 to the LSI inner logic circuit electric power source line 39, which is arranged in the LSI inner logic circuit periphery, via the electric power source wiring 33 in the cell and the electric power source supply port 32.
The electric power supply cell arranged in the conventional LSI peripheral circuit is provided for each type electric power source of the circuit to which the electric power source is supplied such as an input and output circuit or an LSI inner logic circuit.
There is provided a conventional LSI in which an increase in the chip area according to an increase in the number of terminals of LSI is suppressed when an electric power source pad is built in the LSI peripheral circuit element having an empty pad space in which the electrode pad is not arranged. Concerning this conventional LSI, refer to Patent Document 1.
[Patent Document 1]    Unexamined Japanese Patent Publication No. Hei-05-251562
In the case of LSI in which a plurality of input and output circuit cells and electric power supply cells are arranged in the periphery of LSI, data is transmitted from LSI to the external circuit at high speed. Accordingly, there are provided input and output circuits of various standards and electric power source supply circuits of various standards for supplying a reference voltage to the input and output circuits.
However, when a method of transmitting data at high speed, in which the bit width of data is increased, is adopted, the following problems are encountered. The number of the input and output circuit cells is increased. Accordingly, the number of the input and output circuit electric power supply cells for supplying to the input and output circuit cells is increased.
When the components composing LSI are made fine and the ratio of integration is increased and the integrated circuit operates at high speed, electric power consumption in the LSI inner logic circuit is increased. As a result, electric power consumption of the entire LSI is increased, and the number of the necessary LSI inner logic circuit electric power supply cells must be increased in proportion to the electric power consumption.
While LSI is being operated, in order to stabilize operation of the circuit, both the LSI peripheral circuit element and the LSI inner logic circuit must be supplied with a sufficiently high intensity of electric power being protected from a surge in the electric power supply circuit.
When products are inspected, in the case of a finished product inspection or in the case of actually operating the products, the entire circuit elements of LSI including all the input and output circuits are operated. However, in the case of DC inspection of the probing inspection, it is sufficient that a representative cell of the input and output circuit cells is measured, which is based on various interface standards, in the input and output circuit cells arranged in the periphery of LSI. Therefore, different from the finished product inspection, the electric power source cells for supplying electric power to the input and output circuit cells, which are not operated, becomes useless.
In the scan test of the LSI inner logic circuit, it is necessary to instantly operate all the circuits. Therefore, it is necessary to supply a sufficiently high intensity of electric power to the inner logic circuit via the LSI inner logic circuit electric power supply cell. Therefore, it is necessary to provide more electric power supply cells.
However, in general, the number of the LSI inner logic circuit electric power supply cells to be arranged is smaller than that of the input and output circuit electric power supply cells which are arranged by a predetermined ratio with respect to the input and output circuit cells in the periphery of LSI.
In the case of a finished product inspection and also in the case of actually operating the device, these input and output circuit cells 3 take in a signal from the area pad 7 connected to the package. The input and output circuit electric power supply cells 4 take in electric power to be supplied to the input and output circuit cells 3 from the area pad 7 and supply an electric power source voltage to the input and output circuit cells 3 being protected from a surge in the cell.
However, at the time of a probing inspection, these input and output circuit cells 3 are not operated for the following reasons.
(1) The other input and output circuit cells 3 are inspected being represented.
(2) The number of the connection ports with LSI, which the probing inspection device has, is not more than the number of pads of LSI, that is, the device is limited.
Therefore, at the time of the probing inspection, it is unnecessary to supply an electric power source voltage to these input and output circuit cells 3. Therefore, the probing pads connected to the input and output circuit electric power supply cells 4 are not used yet. In this connection, the input and output circuit electric power supply cell 4 itself is necessary for protecting the electric power source from a surge at the time of the finished product inspection. Therefore, it is impossible to get rid of the input and output circuit electric power supply cell 4 for the reason that it is not used in the probing inspection.
In order to enhance the noise resistance property of LSI and in order to reduce an influence given from IR drop, it is an important task to effectively supply electric power to the input and output circuits and the inner logic circuits by using the electric power supply cells, the number of which is limited.
The present invention has been accomplished in view of the above actual circumstances. It is an object of the present invention to provide a semiconductor integrated circuit device in which the number of circuit cells arranged in the periphery of LSI is decreased so as to reduce the chip area.
It is another object of the present invention to enhance the inspection accuracy by increasing the electric power supply paths to the inner logic circuit at the time of the probing inspection and reducing an influence given from IR drop.